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SH67L19
4K 4-bit Micro-controller with LCD Driver
Features Dual clock sources: The SH6610C-based single-chip 4-bit micro-controller - OSC: Crystal oscillator: 32.768kHz, RC oscillator: with LCD driver 32kHz or 131kHz. (selected by Code Option) ROM: 4K X 16 bits - OSCX: Ceramic oscillator: 455kHz, RC oscillator: RAM: 256 X 4 bits 262kHz or 500kHz (400kHz - 600kHz). (Selected by Operation Voltage: 1.2V - 1.7V system register) 4-Level subroutine nesting (include interrupts) Instruction cycle time: One 8-bit Timers with pre-divider circuit - 122.07s for 32.768 kHz crystal One 8-bit Base Timer - 30.53s for 131 kHz RC Warm-up timer for power-on reset - 8.79s for 455kHz ceramic Powerful interrupt sources: - 15.27s for 262kHz RC - External interrupts (Falling or rising edge) - 8s for 500kHz RC - Timer0 interrupts Built-in 2-channel PSG - Base Timer interrupts Built-in alarm generator - PORTB, C interrupts (Falling or rising edge) .com Built-in EL-light driver 24 CMOS bi-directional I/O pins Built-in watchdog timer - PC, PD, PE, PF can switch to segment Built-in Resistor to Frequency converts circuit LCD driver: Up to 6 X 38 dots Two low power operation modes: HALT and STOP - 1/6 duty, 1/3 bias; 1/5 duty, 1/3 bias; 1/4 duty, 1/3 bias Low power consumption or 1/3 duty, 1/2 bias selected by Code Option Bonding option for multi-code software - 17 segment shared with PORTC, D, E, F and CX Available in CHIP FORM Built-in voltage double and treble charge pump circuit
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General Description
The SH67L19 is a single chip micro-controller integrated with 4K mask ROM, SRAM, timer, PSG, alarm, RFC, EL-light, LCD driver, I/O ports. This chip builds in a dual-oscillator to enhance the total chip performance.
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SH67L19
Pad Configuration
PORTD.3 PORTE.0 PORTE.1 PORTE.2 PORTE.3 PORTF.0 PORTF.1 PORTF.2 PORTF.3
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
1 PORTD.2 PORTD.1 PORTD.0 PORTC.3 PORTC.2 PORTC.1 PORTC.0 CX PORTA.3 PORTA.2 PORTA.1 PORTA.0 PORTB.3 PORTB.2 PORTB.1 PORTB.0 2 3 4 5 6 7 8 9 10 11 12 13
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM6 COM5 COM4 COM3
SH67L19
40 39 38 37 36 35 34 33
14 15 16 17
B0 18
19 20 21 22 B1 24 25 26 27 28 29 30 31 OSCO GND COM1 OSCXI OSCXO RESET COM2 OSCI CUP1 CUP2 VP2 TEST VP1
23
32
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VDD
SEG13
Block Diagram
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ROM (4096 X 16) RAM (256 X 4) 8-BIT TIMER0 and Base Timer OSCS
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OSCI OSCO OSCXI OSCXO
CPU CORE
I/O PORTS: (5 X 4)
PORTB (R-F, INT1) PORTC (SEG34 - 37, INT1) PORTD (SEG30 - 33) PORTE (SEG26 - 29) PORTF (SEG22 - 25) PORTA.0 (INT0, ELP ) PORTA.1 (PSG) PORTA.2 (PSG) PORTA.3 (ELC )
PORTA & EXTERNAL INT
LCD RAM R-F convert PSG RESET RESET de-bounce circuit ALARM EL-light
COMMON DRIVER COM [1:6]
SEGMENT DRIVER
SEG [1:21]
CX (SEG38)
CPU OPERATING VOLTAGE GND LCD VOLTAGE GENERATOR
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SH67L19
Pad Description
Pad No. 36 - 56 30 - 35 29, 28 26, 27 25 24 18 Designation SEG1 - SEG21 COM1 - COM6 VP1, VP2 CUP1 - 2 TEST RESET VDD B0 B1 23 21 22 19 20 GND OSCXO OSCXI OSCO OSCI PORTA.3 - PORTA.0 I/O O O P P I I P I I P O I O I I/O Description Segment signal output for LCD display Common signal output for LCD display Power supply pin for LCD driver Connection for voltage doubler capacitor Test pin (Internal pull-low). No connect for user Reset input (internal pull-high selected by Code Option) Power supply Bonding option, internally pull-low Bonding option, internally pull-high Ground pin Oscillator X output Oscillator X input Oscillator output Oscillator input Bit programmable I/O, PORTA.0 could be External Interrupt ( INT0 ), PORTA.0 input is a schmitt trigger PORTA.0, PORTA.3 could be EL-light output PORTA.0 (ELP), PORTA.3 (ELC) .com PORTA.1, PORTA.2 could be buzzer output PORTA.1 (PSG), PORTA.2 (/PSG) Bit programmable I/O, PORTB could be PORT Interrupt ( INT1 ) PORTB.0 - PORTB.2 shared with RX1 - 3, PORTB.3 shared with RXB Bit programmable I/O, PORTC could be PORT Interrupt ( INT1 ) PORTC.3 - PORTC.0 shared with LCD Seg34 - 37 Bit programmable I/O, PORTD.3 - PORTD.0 shared with LCD Seg30 - 33 Bit programmable I/O, PORTE.3 - PORTE.0 shared with LCD Seg26 - 29 Bit programmable I/O, PORTF.3 - PORTF.0 shared with LCD Seg22 - 25 R-F converter counter input pin, shared with Seg38
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10 - 13
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14 - 17 5-8 1-4 61 - 64 57 - 60 9
PORTB.3 - PORTB.0 PORTC.3 - PORTC.0 PORTD.3 - PORTD.0 PORTE.3 - PORTE.0 PORTF.3 - PORTF.0 CX
I/O I/O I/O I/O I/O I/O
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SH67L19
Functional Description
1. CPU The CPU core contains the following function blocks: Program Counter, ALU, Carry Flag, Accumulator, Table Branch Register (TBR), Data Pointer (INX, DPH, DPM and DPL), and Stack. 1.1. PC (Program Counter) The PC is used for ROM addressing consisting of 12-bits: Page Register (PC11), and Ripple Carry Counter (PC10 PC0). The program counter normally increases by one (+1) with each execution of an instruction except in the following cases: (1) When executing a jump instruction (such as JMP, BA0, BC), (2) When executing a subroutine call instruction (CALL), (3) When an interrupt occurs, (4) When the chip is at INITIAL RESET. The program counter is loaded with data corresponding to each instruction. The unconditional jump instruction (JMP) can be set at 1-bit page register for higher than 2K. Program Counter can only address a 4K of program ROM. Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM) Decision (BA0, BA1, BA2, BA3, BAZ, BC) Logic shift (SHR) The Carry Flag (CY) holds the arithmetic operation ALU overflow. During interrupt or call instruction, carry is pushed into stack and restored from stack by RTNI. It is unaffected by an RTNW instruction. 1.3. Accumulator The accumulator is a 4-bit register holding the results of the arithmetic logic unit. In conjunction with the ALU, data transfers between the accumulator and system register, LCD RAM, or data memory can be performed.
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1.4. Stack This group of registers is used to save the contents of CY & PC (11 - 0) sequentially with each subroutine call or interrupt. It is organized 13 bits X 4 levels. The MSB is saved for CY. Four levels are the maximum allowed for subroutine calls and interrupts. The contents of Stack are returned sequentially to the PC with the return instructions (RTNI/RTNW). Stack is operated 1.2. ALU and CY on a first-in, last-out basis. This 4-level nesting includes both The ALU performs arithmetic and logic operations. subroutine calls and interrupts requests. Note that program It provides the following functions: execution may enter an abnormal state if the number of calls .com Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI) and interrupt requests exceeds 4, where then the bottom of Decimal adjustment for addition/subtraction (DAA, DAS), stack will be shifted out. 2. ROM The SH67L19 can address 4K X 16 bit of program area $000 to $FFF. There is an area from addresses $000 through $004 reserved for special interrupts service routines such as starting vector address. Address 000H 001H 002H 003H 004H Instruction JMP Instruction JMP Instruction JMP Instruction JMP Instruction JMP Instruction Function Jump to RESET service routine Jump to external interrupt service routine ( INT0 ) Jump to Timer0 service routine Jump to Base Timer service routine Jump to PORTB, C service routine ( INT1 )
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SH67L19
3. RAM Built-in SRAM contains general-purpose data memory, LCD RAM, and system registers. Direct addressing in one instruction can access them. The following is the memory allocation map: $000 - $01F: System register and I/O $020 - $11F: Data memory (256 X 4bits, divide into 3 banks) $300 - $325, $330 - $355: LCD RAM $360 - $368: PSG control registers (9 X 4 bits) $269 - $26D: R-F counter registers (5 X 4 bit) The Configuration of System Register Address $00 $01 $02 $03 $04 $05 $06 Bit3 IEX IRQX TM0.3 BTM.3 T0L.3 T0H.3 ENX Bit2 IET0 IRQT0 TM0.2 BTM.2 T0L.2 T0H.2 ELON Bit1 IEBT IRQBT TM0.1 BTM.1 T0L.1 T0H.1 LCDOFF Bit0 IEP IRQP TM0.0 BTM.0 T0L.0 T0H.0 PSGON R/W R/W R/W R/W R/W R/W R/W R/W Remarks Interrupt enable flags Interrupt request flags Timer0 mode register Base timer mode register Timer0 load/counter low nibble Timer0 load/counter high nibble Bit0: PSG on/off control Bit1: LCD on/off control Bit2: EL-light on/off control Bit3: R-F convert counter on/off control Bit0 - 2: count resister1 - 3 enable Bit3: set PORTB as R-F converter PORTA data register PORTC data register PORTD data register PORTE data register PORTF data register Table branch register Index register (INX) Data pointer for INX low nibble Data pointer for INX middle nibble Data pointer for INX high nibble Bit0: Set CX as LCD segment 38 Bit1: Select LCD segment output high or low EL-LIGHT mode control Bit2: ELP driver output frequency control Bit3: EL-LIGHT driver frequency select Bit0: Heavy Load Mode Bit1: Turn on OSCX oscillator Bit2: CPU clocks select (1: OSCX /0: OSC) Bit3: OSCX type selection Initial Value 0000 0000 0000 0000 0000 0000 0010
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$07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12
O/RF PA.3 PB.3 PC.3 PD.3 PE.3 PF.3 TBR.3 INX.3 DPL3 -
RX3EN PA.2 PB.2 PC.2 PD.2 PE.2 PF.2 TBR.2 INX.2 DPL2 DPM.2 DPH.2
RX2EN PA.1 PB.1 PC.1 PD.1 PE.1 PF.1 TBR.1 INX1 DPL1 DPM.1 DPH.1
RX1EN PA.0 PC.0 PD.0 PE.0 PF.0 TBR.0 INX.0 DPL0 DPM.0 DPH.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0000 0000 0000 0000 0000 0000 0000 -
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.com data register R/W PB.0 PORTB
$13
ELF
ELPF
SOH/L
S/CX
R/W
0001
$14
OXS
OXM
OXON
HLM
R/W
0000
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SH67L19
System Register (Cont.) Address Bit3 PULLEN $15 B1 B0 R Bit2 PH/PL Bit1 Bit0 R/W R/W Remarks Bit0, 1: Bonding Option Bit2: Port pull high (falling edge interrupt) or pull low (rising edge interrupt) select Bit3: pull high/low enable control Bit0: Set PORTC as LCD segment Bit1: Set PORTD as LCD segment Bit2: Set PORTE as LCD segment Bit3: Set PORTF as LCD segment Bit3: WDT time-out bit (write one to reset WDT) Bit2 - 0: Watchdog timer on/off control (initial: 010, watchdog on) Set PORTA to be output port Set PORTB to be output port Set PORTC to be output port Bit0: Set PORTD to be output port Bit1: Set PORTE to be output port Bit2: Set PORTF to be output port When PORTC - PORTF used as input, their input state control Used in key matrix's application When PORTA, PORTB used as input, their input state control Used in key matrix's application R-F counter register nibble 1 (bit0 - 3) R-F counter register nibble 2 (bit4 - 7) R-F counter register nibble 3 (bit8 - 11) R-F counter register nibble 4 (bit12 - 15) R-F counter register nibble 5 (bit16 - 19) PSG channel 1 low nibble PSG channel 1high nibble Bit3: channel 1 mode control PSG channel 2 nibble 1 or alarm output PSG channel 2 nibble 2 PSG channel 2 nibble 3 PSG channel 2 nibble 4 Bit3: channel 2 mode control Bit0, Bit1: Channel 1, 2 enable Bit2, Bit3: volume control PSG1 and PSG2 Pre-scalar Bit0: PSG clock source select. Bit1: Alarm on or off. Bit2: OSCX RC oscillator select Initial Value 0010
$16
O/S4
O/S3
O/S2
O/S1
R/W
1111
$17 $18 $19 $1A $1B $1C
WDT
WT2
WT1
WT0
W W W W W W W
1010 0000 0000 0000 -000 0000 --00
PACR.3 PACR.2 PACR.1 PACR.0 PBCR.3 PBCR.2 PBCR.1 PBCR.0 PCCR.3 PCCR.2 PCCR.1 PCCR.0 PCIN PFCR PDIN PECR PEIN PAIN RF1.3 RF2.3 RF3.3 RF4.3 RF5.3 C1.3 CM1 C2.3 C2.7 C2.11 CM2 VOL1 P2.1 RF1.2 RF2.2 RF3.2 RF4.2 RF5.2 C1.2 C1.6 C2.2 C2.6 C2.10 C2.14 VOL0 P2.0 F262 RF1.1 RF2.1 RF3.1 RF4.1 RF5.1 C1.1 C1.5 C2.1 C2.5 C2.9 C2.13 CH2EN P1.1 ALM PDCR PFIN PBIN RF1.0 RF2.0 RF3.0 RF4.0 RF5.0 C1.0 C1.4 C2.0 C2.4 C2.8 C2.12 CH1EN P1.0 SEL
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$1D $1E - 1F $269 $26A $26B $26C $26D $360 $361 $362 $363 $364 $365 $366 $367 $368
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Reserved .com R/W R/W R/W R/W R/W W W W W W W W W W 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
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SH67L19
4. Data Memory The general-purpose data memory is organized as 256 X 4 bits. Because of its static feature, the RAM can retain data after the CPU enters STOP or HALT mode. 5. Oscillator Circuit 5.1. Circuit Configuration The SH67L19 has two on-chip oscillation circuits OSC and OSCX. OSC is a low frequency crystal (32.768kHz) or RC (32kHz or 131kHz) oscillator determined by the Code Option. This is designed for low frequency operation. OSCX is a high frequency ceramic (455kHz) or RC (262kHz or 500kHz) oscillator. It is designed for high frequency operation. It is possible to select the high speed CPU processing by a high frequency clock and select low power operation by low operation clock. At the start of reset initialization, OSC is turned on and OSCX is turned off. Immediately after reset initialization, the OSC is automatically selected as the system clock input source. When starting the reset, the system clock will be set as OSC, and the frequency is 32.768kHz crystal, 32kHz RC or 131kHz RC. After the initialization, users can turn on the OSCX. Then OSC can be switched to OSCX as system clock, and the two-oscillation circuit can be switch randomly. If the OSCX is not used, the OSCXI pin must be connected to GND. OSC and OSCX will be turned off in STOP mode. When waking up from STOP, the system clock will be set as OSC. After waking up from STOP, the OSC can be switched to OSCX as system clock, if user wants to use high frequency clock. 5.2. Control of Oscillator The oscillator control register configuration is shown as follows: Address Bit3 OXS Bit2 OXM Bit1 OXON Bit0 HLM Remarks ... Bit1: Turn on OSCX oscillator Bit2: CPU clock select (1: OSCX /0: OSC) Bit3: OSCX type selection
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$14
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OXON: OSCX oscillation on/off. 0: Turn-off OSCX oscillation OXM: switching system clock. 0: select OSC as system clock OXS: OSCX oscillator type selection. 0: OSCX set as Ceramic oscillation
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1: Turn-on OSCX oscillation 1: select OSCX as system clock 1: OSCX set as RC oscillator
5.3. Programming Notes It takes at least 5 ms for the OSCX oscillation circuit to turn on until the oscillation stabilizes. When switching the CPU system clock from OSC to OSCX, the user must wait a minimum of 5ms since the OSCX oscillation is running. However, the start time varies with respect to oscillator characteristics and the condition of use. Thus the wait time depends on the application. When switching from OSCX to OSC, and turning off OSCX in one instruction. The OSCX turn off control will be delayed for one instruction cycle automatically to prevent CPU operation error.
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SH67L19
5.4. Timing of System Clock Switching
6. System Clock The system clock varies as the clock source changes. The following table shows the instruction execution time according to each frequency of the system clock source. 32.768k (OSC) Cycle time 7. I/O PORT 122.07 s 131k (OSC) 30.53 s 455k (OSCX) 8.79 s 262k (OSCX) 15.27 s 500k (OSCX) 8 s
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The SH67L19 has 24 CMOS bi-directional I/O ports: PORTA - PORTF. Each I/O pin contains pull-high and pull-low MOS controllable through programming. The PORT control register controls the ON/OFF of the output buffer. I/O ports of the SH67L19 can be accessed by read/write the system register. Users can output any value to any I/O port bit at any time. The circuit configuration of PORTA - F is shown in Figure.com 1. 7.1. Controlling the Pull-high/Pull-low MOS PORTA - PORTF contain pull-high/low MOS controlled by the program. System register $15 Bit3, Bit2 controls pull-high/pull-low MOS on or off. Pull-high/pull-low MOS is also controlled by the port data registers of each port as well. Thus the pull-high/pull-low MOS can be turned on/off individually. Port Mode Register (PMOD) Address $15 Bit3 PULLEN Bit2 PH/PL Bit1 B1 Bit0 B0 Remarks ... Bit2: Port pull-high/pull-low set Bit3: Port pull-up/pull-low enable control
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PULLEN: Pull high/low enable 0: Disable pull-high/low MOS PH/PL: select pull high or pull low 0: port pull low resistor on
1: Enable pull-high/low MOS 1: port pull high resistor on
7.2. Port Interrupt ( INT1 ) The PORTB and PORTC are used as port interrupt sources (falling or rising edge), only the input port can generate PORT interrupt. When PULLEN = 1, PH/PL = 1 and IEP is set to "1", any one of the PORTB and PORTC input pin transitions from VDD to GND will generate an interrupt request. When PULLEN = 1, PH/PL = 0 and IEP is set to "1", any one of the PORTB and PORTC input pin transitions from GND to VDD will generate an interrupt request. When PORTB are used as R-F converter (O/RF = 1), the PORTB interrupt were disabled even the IEP is set to "1". When PORTC are used as LCD outputs (O/S1 = 1), the PORTC interrupt are disabled also even the IEP is set to "1".
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SH67L19
7.3. External Interrupt ( INT0 ) The PORTA.0 is used as external interrupt sources (falling or rising edge), only PORTA.0 is input port can generate an external interrupt. When PULLEN = 1, PH/PL = 1 and IEX is set to "1", PORTA.0 input pin transitions from VDD to GND will generate an interrupt request. When PULLEN = 1, PH/PL = 0 and IEX is set to "1", PORTA.0 input pin transitions from GND to VDD will generate an interrupt request. When PORTA.0 is used as ELP, the External interrupt is disabled even the IEX is set to "1". Note: If internal PORT pull-high and pull-low resistor is not used, the SH67L19 will respond PBC or PORTA.0 interrupt by connecting resistors to VDD or GND externally. 7.4. Port I/O Control Register: Address $18 $19 $1A $1B Bit3 PACR.3 PBCR.3 PCCR.3 Bit2 PACR.2 PBCR.2 PCCR.2 PFCR Bit1 PACR.1 PBCR.1 PCCR.1 PECR Bit0 PACR.0 PBCR.0 PCCR.0 PDCR
I/O control register: PACR.X - PCCR.X (X = 0, 1, 2, 3) by bit control 1: Defined as an output terminal. 0: Defined as an input terminal (default). PDCR, PECR, PFCR by port control 1: Defined the port as output terminal. 0: Defined the port as input terminal (default).
ELON register Pull-high PMOS PULL UP PH/L Pull-high PMOS
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PSGON register PULL UP PH/L
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PORTA.1, PORTA.2 PORT CONTROL REGISTER PORT DATA REGISTER
PORT CONTROL REGISTER PORT DATA REGISTER
PORTA.0, PORTA.3
DATA INPUT
RD-INPUT Pull-low PMOS PSG OUTPUT PORTA.1, PORTA.2 (for reference only) O/RF register PULL UP PH/L Pull-high PMOS
DATA INPUT
RD-INPUT Pull-low PMOS EL OUTPUT PORTA.0, PORTA.3 (for reference only) O/S register PULL UP PH/L Pull-high PMOS
PH/L PULL UP
PH/L PULL UP
PORT CONTROL REGISTER PORTB PORT DATA REGISTER
PORT CONTROL REGISTER PORT DATA REGISTER PORTC - PORTF
DATA INPUT
RD-INPUT Pull-low PMOS
DATA INPUT
RD-INPUT Pull-low PMOS SEGMENT OUTPUT PORTC - PORTF (for reference only)
PH/L PULL UP R-F convert PORTB (for reference only)
PH/L PULL UP
Figure. 1
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SH67L19
7.5. Heavy Load Mode (HLM) Address $14 Bit3 OXS Bit2 OXM Bit1 OXON Bit0 HLM Remarks Bit0: Heavy Load Mode ...
HLM: 0 = Heavy load protection mode is released 1 = Heavy load protection mode is set. The MCU has a heavy load protection circuit when the battery load becomes heavy, such as, when an external buzzer sounds or an external speaker is turned on. In this mode, the low frequency crystal oscillator circuit and high frequency ceramic circuit have been backed up for high gain. When this mode is set, more power would be provided to oscillator circuit. Unless it is necessary, do not set this mode by software since entering the mode would delay an instruction. Please activate the heavy load driving only after setting the HLM for at least one instruction wait cycle through the software. The following shows the programming setting.
HLM
0 1
ON
HEAVYLOAD
OFF
1 Instruction Cycle Time
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7.6. Ports as Key Matrix The SH67L19's I/O can make up the key matrix and PORTC - PORTF can be used as a LCD segment output at the same time. In this application, users should control that scanning key matrix to share the timing of LCD display and will not affect the LCD display. Only when user scan the key matrix, all Ports are used as I/O; otherwise PORTC - PORTF are used as LCD segment .com outputs to drive the LCD panel. The Ports used as I/O or segment is controlled by software. In scan key application, when user doesn't execute the operation of scan key, Ports not sharing the LCD segment output should be set as I/O, and disable it's pull-high/pull-low resistor and input/output access by the corresponding bit of the write system register ($18 - $1D). Executing the above operation can prevent inputting the LCD voltage to the general I/O Ports and the pull-high/pull-low or output of the port affect the LCD segment's waveform. When users wants to scan key, all ports which make up of the key matrix should be used as general I/O. The ports' pull-high/pull-low resistor and input access should be enabled by clearing the corresponding bit of the system register ($1C, $1D). Key Matrix's Input Ports Control Register Address $1C $1D Bit 3 PCIN Bit 2 PDIN Bit 1 PEIN PAIN Bit 0 PFIN PBIN R/W W W Remarks Control PORTC - PORTF input and output access enable or disable. Used in key matrix's application. Control PORTA - PORTB input and output access enable or disable. Used in key matrix's application.
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PAIN...PFIN: In the key matrix's application, control PORTA - PORTF input and output access. 0: Enable PORTA - PORTF pull-high/pull-low resistor and I/O access, Ports in normal state 1: Disable PORTA - PORTF pull-high/pull-low resistor and it's I/O access
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SH67L19
8. Programmable Sound Generator (PSG) PSG has channel1 and channel2. Channel 1 is a 7-bit pseudo random counter. Channel 2 is a 15-bit pseudo random counter. Mode bits CM1, CM2 determine which of the two counters will be a noise or a tone generator. To reduce power consumption, disable the sound effect generator during STOP mode. Channel 2 TONE mode is same as Channel 1. (7-bit pseudo-random counter). PSG also provides alarm function. The alarm on or off controlled by register (ALM). This eliminates some programming codes. Address $360 $361 $362 $363 $364 $365 $366 $367 Bit 3 C1.3 CM1 C2.3 C2.7 C2.11 CM2 VOL1 P2.1 Bit 2 C1.2 C1.6 C2.2 C2.6 C2.10 C2.14 VOL0 P2.0 F262 Bit 1 C1.1 C1.5 C2.1 C2.5 C2.9 C2.13 CH2EN P1.1 ALM Bit 0 C1.0 C1.4 C2.0 C2.4 C2.8 C2.12 CH1EN P1.0 SEL Remarks PSG channel 1 low nibble PSG channel 1high nibble Bit3: channel 1 mode control PSG channel 2 nibble 1 or alarm output PSG channel 2 nibble 2 PSG channel 2 nibble 3 PSG channel 2 nibble 4 Bit3: channel 2 mode control Bit0: Channel 1 enable Bit1: Channel 2 enable Bit2, Bit3: volume control (initially 0, no sound) PSG1 and PSG2 Pre-scalar Bit0: PSG clock source select. Bit1: Alarm on or off. Bit2: OSCX RC oscillator select R/W W W W W W W W W W
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$368
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PORTA.1 and PORTA.2 Output Control and Vol. Control .com When PSGON = 1 and ALM=0, the PORTA.1 PORTA.2 is used as PSG output and controlled by the volume control bit into 4 volume levels output. When PSGON = 1 and ALM = 1, the alarm function will open, PORTA.1 PORTA.2 is used as alarm output. PSGON 0 1 1 ALM X 0 1 Function PORTA.1 and PORTA.2 as I/O Port PORTA.1 and PORTA.2 as PSG output PORTA.1 and PORTA.2 as Alarm output VOL1 0 0 1 1 VOL0 0 1 0 1 Vol. Level 1 (no sound) 2 3 4
PSG Two Channels Mode Control When using PSG output (PSGON = 1 and ALM = 0), two channels' mode is controlled by CM1 ($361 bit3), CM2 ($365 bit3): CM1: 1: channel 1 is noise generator. 0: channel 1 is tone generator. CM2: 1: channel 2 is noise generator. 0: channel 2 is tone generator. Channel 1 Channel 1 is constructed by a 7-bit pseudo random counter. Channel 1 is enabled/disabled by CH1EN. It can be a 7-bit wide-band noise generator or a 7-bit sound generator. It can create either sound frequency by writing value N in C1.6 - C1.0. Channel 2 Channel 2 is constructed by a 15-bit pseudo random counter. Channel 2 is enabled/disabled by CH2EN. It can be a 15-bit wide-band noise generator or a 7-bit sound generator. It can create either sound frequency by writing value N in C2.8 - C2.14.
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SH67L19
PSG Clock Control Register Address $367 $368 Bit 3 P2.1 Bit 2 P2.0 F262 Bit 1 P1.1 ALM Bit 0 P1.0 SEL Remarks PSG1 and PSG2 Pre-scalar Bit0: PSG clock source select Bit1: Alarm on or off Bit2: OSCX RC oscillator select
P1.0, P1.1 and P2.0, P2.1 select the pre-scalar of PSG actual clock P1.1, P2.1 0 0 1 1 P1.0, P2.0 0 1 0 1 Pre-scalar Divide Ratio 1 2 4 8 Clock Source 32 kHz 32 kHz 32 kHz 32 kHz Actual Clock 32 kHz 16 kHz 8 kHz 4 kHz
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SEL: select OSC or OSCX is used to generate PSG clock source 0: PSG clock source is provided by OSC (low frequency clock) 1: PSG clock source is provided by OSCX (high frequency clock) F262: OSCX RC oscillator frequency selection 0: Use 500k RC as oscillator 1: Use 262k RC as oscillator If the OSCX is used as system clock, the value of bit "F262" must correspond to the OSCX's frequency, otherwise PSG clock source will not be true. No matter which oscillator and frequency is selected to provide PSG clock source, the PSG clock source is always equal 32kHz. PSG Sub-Block Diagram:
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SEL F262 code option
OSC CLK-SLECTOR OSCX
clock source for PSG 32kHz
32kHz SELECTOR 32k PSG clock source 1/2 16kHz 1/4 8kHz 1/8 4kHz PSG-CLK
PSG-CLK
1/N
PSG CLK
P.x 0
P.x 1
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Example: A user uses 500kHz RC clock, and wants to create a tone `C3' whose frequency are 130.81Hz. If the user writes 00H to P.1 and P.0, and sets OXON, OXM, OXS = 1, so that the system clock is 500kHz, PSG clock source is 32kHz and PSG-CLK = 32kHz, the value of N is 32k/130.81/2 = 122.3, looking up 122 in the table, and the corresponding initial data of LSFR is 20H. If the user writes 01H to P.1 and P.0, then the PSG-CLK is 16kHz, the value of N is 16k/130.81/2 = 61.2, and the initial data is 49H. If the user writes 10H to P.1 and P.0, then the PSG-CLK is 8kHz, the value of N is 8k/130.81/2 = 31, and the initial data is 4BH. If the user writes 11H to P.1 and P.0, then the PSG-CLK is 4kHz, the value of N is 4k/130.81/2 = 15, and the initial data is 15H. When the tone frequency is too low, the expected value of N maybe greater than 127, and the counter cannot create such value. A better way is to select a low PSG-CLK. For example, for the frequency of tone `C1' is 32.7Hz, if the PSG-CLK is greater than 8kHz, the expected N is greater than 127, but the 4kHz PSG-CLK can create this tone. According to the previous illustration, users can make a music table by themselves. If a user selects any oscillator and PSG-CLK, the music table is given as follows. Music Table1: Following is the music scale reference table for channel 1(or channel 2) under Actual Clock = 32kHz. Note C3 D3 E3 F3 Ideal freq. 130.81 146.83 164.81 174.61 195.99 220.00 246.94 261.62 293.66 329.62 349.22 N 122 109 97 92 82 73 65 61 54 49 46 LSFR (C1.6 - C1.0) (C2.14 - C2.8) 20 51 45 33 27 21 44 49 5A 5B 5E Real freq. 131.15 146.79 164.95 173.91 195.12 219.18 246.15 262.30 296.30 326.53 347.83 Error % 0.26% -0.03% 0.08% -0.40% -0.44% -0.37% -0.32% 0.26% 0.90% -0.94% -0.40% Note G4 A4 B4 C5 D5 E5 F5 Ideal freq. 392.0 440.0 493.9 523.2 587.3 659.2 698.4 784.0 880.0 987.7 1046.5 N 41 36 32 31 27 24 23 20 18 16 15 LSFR (C1.6 - C1.0) (C2.14 - C2.8) 58 1A 25 4B 3B 5C 39 4C 32 4A 15 Real freq. 390.24 444.44 500.00 516.13 592.59 666.67 695.65 800.00 888.89 1000.00 1066.67 Error % -0.44% 1.01% 1.24% -1.36% 0.90% 1.13% -0.40% 2.04% 1.01% 1.24% 1.93%
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G3 A3 B3 C4 D4 E4 F4
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G5 A5 B5 C6
Music Table2: Following is the music scale reference table for channel 1(or channel 2) under Actual Clock = 16kHz. Note C2 D2 E2 F2 G2 A2 B2 C3 D3 E3 F3 Ideal freq. 65.41 73.41 82.41 87.31 98.00 110.00 123.47 130.81 146.83 164.81 174.61 N 122 109 97 92 82 73 65 61 54 49 46 LSFR (C1.6 - C1.0) (C2.14 - C2.8) 20 51 45 33 27 21 44 49 5A 5B 5E Real freq. 65.57 73.39 82.47 86.96 97.56 109.59 123.08 131.15 148.15 163.27 173.91 Error % 0.26% -0.03% 0.08% -0.40% -0.44% -0.37% -0.32% 0.26% 0.90% -0.94% -0.40% Note G3 A3 B3 C4 D4 E4 F4 G4 A4 B4 C5 Ideal freq. 195.99 220.00 246.94 261.62 293.66 329.62 349.22 391.99 439.99 493.87 523.24 N 41 36 32 31 27 24 23 20 18 16 15 LSFR (C1.6 - C1.0) (C2.14 - C2.8) 58 1A 25 4B 3B 5C 39 4C 32 4A 15 Real freq. 195.12 222.22 250.00 258.06 296.30 333.33 347.83 400.00 444.44 500.00 533.33 Error % -0.44% 1.01% 1.24% -1.36% 0.90% 1.13% -0.40% 2.04% 1.01% 1.24% 1.93%
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Music Table3: Following is the music scale reference table for channel 1(or channel 2) under Actual Clock = 8kHz. Ideal freq. 32.70 36.71 41.20 43.65 49.00 55.00 61.73 65.41 73.41 82.41 87.31 N 122 109 97 92 82 73 65 61 54 49 46 LSFR (C1.6 - C1.0) (C2.14 - C2.8) 20 51 45 33 27 21 44 49 5A 5B 5E Real freq. 32.79 36.70 41.24 43.48 48.78 54.79 61.54 65.57 74.07 81.63 86.96 Error % 0.26% -0.03% 0.08% -0.40% -0.44% -0.37% -0.32% 0.26% 0.90% -0.94% -0.40% Note G2 A2 B2 C3 D3 E3 F3 G3 A3 B3 C4 Ideal freq. 98.00 110.00 123.47 130.81 146.83 164.81 174.61 195.99 220.00 246.94 261.62 N 41 36 32 31 27 24 23 20 18 16 15 LSFR (C1.6 - C1.0) (C2.14 - C2.8) 58 1A 25 4B 3B 5C 39 4C 32 4A 15 Real freq. 97.56 111.11 125.00 129.03 148.15 166.67 173.91 200.00 222.22 250.00 266.67 Error % -0.44% 1.01% 1.24% -1.36% 0.90% 1.13% -0.40% 2.04% 1.01% 1.24% 1.93%
Note C1 D1 E1 F1 G1 A1 B1 C2 D2 E2 F2
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Music Table4: Following is the music scale reference table for channel 1(or channel 2) under Actual Clock = 4kHz. Note C0 D0 E0 F0 G0 A0 B0 C1 D1 E1 F1 Ideal freq. 16.35 18.35 20.60 21.83 24.50 27.50 30.87 32.70 36.71 41.20 43.65 N 122 109 97 92 82 73 65 61 54 49 46 LSFR (C1.6 - C1.0) (C2.14 - C2.8) 20 51 45 33 27 21 44 49 5A 5B 5E Real freq. 16.39 18.35 20.62 21.74 24.39 27.40 30.77 32.79 37.04 40.82 43.48 Error % 0.26% -0.03% 0.08% -0.40% -0.44% -0.37% -0.32% 0.26% 0.90% -0.94% -0.40%
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Real freq. 48.78 55.56 62.50 64.52 74.07 83.33 86.96 100.00 111.11 125.00 133.33 Error % -0.44% 1.01% 1.24% -1.36% 0.90% 1.13% -0.40% 2.04% 1.01% 1.24% 1.93%
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Note G1 A1 B1 C2 D2 E2 F2 G2 A2 B2 C3 freq. 49.00 55.00 61.73 65.41 73.41 82.41 87.31 98.00 110.00 123.47 130.81
N 41 36 32 31 27 24 23 20 18 16 15
LSFR (C1.6 - C1.0) (C2.14 - C2.8) 58 1A 25 4B 3B 5C 39 4C 32 4A 15
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The value N of divider1 is corresponding to the REG C1.6 - C1.0 or REG C2.14 - C2.8 as shown in the following table: LSFR (C1.6 - C1.0) (C2.14 - C2.8) 01 02 04 08 10 20 41 03 06 0C 18 30 N 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 LSFR (C1.6 - C1.0) (C2.14 - C2.8) 16 2C 59 33 67 4E 1D 3A 75 6A 54 29 53 27 4F 1F 3E 7D 7A 74 68 50 21 43 07 0E 1C 38 71 62 44 09 N 95 94 93 92 91 90 89 88 87 86 85 84 83 82 LSFR (C1.6 - C1.0) (C2.14 - C2.8) 12 24 49 13 26 4D 1B 36 6D 5A 35 6B 56 2D N 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 LSFR (C1.6 - C1.0) (C2.14 - C2.8) 4B 17 2E 5D 3B 77 6E 5C 39 73 66 4C 19 32 65 4A 15 2A 55 2B 57 2F 5F 3F 7F 7E 7C 78 70 60 40 N 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
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61 42 05 0A 14 28 51 23 47 0F 1E 3C 19 72 64 48 11 22 45 0B
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80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 37 6F 5E 3D 7B 76 6C 58 31 63 46 0D 1A 34 69 52 25
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Alarm Generator Mode: When PSGON = 1 and ALM = 1, the circuit will provide the alarm carrier frequency (4kHz or 2 kHz selected by Code Option) and Channel 2 will provide the alarm envelope signal. The channel 2 low nibble C2.0 - C2.3 will be the alarm control register. Alarm control register ($362): C2.3 0 X X X 1 C2.2 0 X X 1 X C2.1 0 X 1 X X C2.0 0 1 X X X Alarm output control DC envelop 1Hz output 2Hz output 4Hz output 8Hz output
The programming alarm waveform is shown below:
8Hz 4Hz 2Hz 1Hz
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BD OUTPUT 2K or 4k $362 = $0 ALM = 1 $362= $8 ALM = 1 $362 = $C ALM = 1 $362 = $A ALM = 1 $362 = $F ALM = 1
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9. Timer 0 The SH67L19 has one 8-bit timer. The timer consists of an 8-bit up counter and an 8-bit preload register. The timers provide the following functions: - Programmable internal timer function - Read the counter values 9.1. Timer 0 Configuration and Operation The timer 0 consists of an 8-bit write-only timer load register (TL0L, TL0H) and an 8-bit read-only timer counter (TC0L, TC0H). Each has low order digits and high order digits. Writing data into the timer load register (TL0L, TL0H) can initialize the timer counter. Write the low-order digit first and then the high-order digit. The timer counter is loaded with the content of the load register automatically when the high order digit is written or counts overflow happens. The timer overflow will generate an interrupt, if the interrupt enable flag is set. The timer can be programmed in several different system clock sources by setting the Timer Mode register (TM0). Timer 0 reads and writes operations follow these rules: Write Operation Low nibble first High nibble to update the counter 9.2. Timer0 Mode Register (TM0) The 8-bit counter counts pre-scaler overflow output pulses. TM0 are 4-bit registers used for timer control as shown in Table 1.2 When the OSC used as system clock, the timer0's clock source can't be selected by TM0.3, the timer0's clock source is system clock (OSC/4). See in Table1. Table 1. Timer0 Mode Registers ($02) TM0.3 0 0 0 0 0 0 0 0 TM0.2 0 0 0 0 1 1 1 1 TM0.1 0 0 1 1 0 0 1 1 TM0.0 0 1 0 1 0 1 0 1 Read Operation High nibble first Low nibble follows
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Prescaler /2048 /512 /128 /32 /8 /4 /2 /1
Clock Source System clock System clock System clock System clock System clock System clock System clock System clock
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When the OSCX is used as system clock, the TM0.3 can select timer0's clock source. See in Table 2 TM0.3 = 0: timer0 clock source is system clock (OSCX/4) TM0.3 = 1: timer0 clock source is generated by OSC; clock source is 32k (32.768kHz crystal, 32kHz RC or RC 131kHz/4) Table 2. Timer0 Mode Registers ($02) TM0.3 0 0 0 0 0 0 0 0 1 1 1 TM0.2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TM0.1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TM0.0 0 1 0 1 0 1 0 1 0 1 0 1 Prescaler /2048 /512 /128 /32 /8 /4 /2 /1 /2048 /512 /128 /32 /8 /4 /2 /1 Clock Source System clock System clock System clock System clock System clock System clock System clock System clock 32k 32k 32k 32k 32k 32k 32k 32k
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1 1 1 1 1 9.3. Warm-up Counter
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1 0 1
0
In 32k RC mode, the warm-up counter prescaler is divided by 2 (1024) 12 In 131k RC mode, the warm-up counter prescaler is divided by 2 (4096) 13 In CRYSTAL mode, the warm-up counter prescaler is divided by 2 (8192)
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10. Base Timer The MCU has a base timer. The base timer clock source is 32k (32.768kHz crystal, 32kHz RC or RC 131kHz/4). After MCU is reset, it counts at every clock-input signal. When it counts to $FF, right after next clock input, the counter counts to $00 and generates an overflow. This causes the interrupt of base timer interrupt request flag to 1.Therefore, the base timer can function as an interval timer periodically, generating overflow output as every 256th clock signal output. The timer accepts 4kHz clock, and base timer generates an accurate timing interrupt. This clock-input source is selected by BTM register. Address $03 Bit3 BTM.3 Bit2 BTM.2 Bit1 BTM.1 Bit0 BTM.0 Remarks Base timer mode register
BTM.3 = 0: Disable the base timer BTM.2 = 0: Non reset the base timer
BTM.3 = 1: Enable the base timer BTM.2 = 1: reset the base timer
BTM[3] 8 Bit base timer counter reset /16 BTM [2]
MPX /1 4.096kHz /4 /8
32.768kHz
/8
4Bit Scaler
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BTM.1 0 0 1 1 BTM.0 0 1 0 1 Prescaler Ratio /1 /4 /8 /16 Clock Source 4.096kHz 4.096kHz 4.096kHz 4.096kHz
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11. Watchdog Timer The SH67L19 has a Watchdog-Timer. The input clock of the watchdog timer is fetched from the low frequency oscillator (OSC). So the WDT will not run in the STOP mode. The SH67L19 will generate a RESET condition when the Watchdog timing-out. The Watchdog can be enabled or disabled permanently by the system register ($17)'s bit2 - 0. To prevent it from timing-out and generating a device RESET condition, users should write bit3 of system register $17 as "1" before timing-out. If a longer timing-out period is desired, a prescaler with a division ratio of up to 1:2048 can be assigned to the WDT under software controlled by writing to the TM0 register ($02). System Register $17 Address $17 Bit 3 WDT Bit 2 WT2 Bit 1 WT1 Bit 0 WT0 Remarks Bit3: Watchdog timer reset/flag. (write 1 to reset WDT) Bit2 - 0: Watchdog timer on/off control Power On 1010
WT2 - WT0 = 010 (defualt), 000, 001, 011, 100 110, 111: watchdog timer is enabled WT2 - WT0 = 101: watchdog timer is disable
32.768kHz crystal or 131kHz RC/4
TM0
Internal
SCALER_1
/2048 /1 /2 /4
PRESCALER
/8
/32 /128
/512
/2048
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Prescaler Divide Ratio: TM0.2 1 1 1 1 0 0 0 0 TM0.1 1 1 0 0 1 1 0 0 TM0.0 1 0 1 0 1 0 1 0 Prescaler Divide Ratio 1:1 1:2 1:4 1:8 1:32 1:128 1:512 1:2048 (Power on initial)
Final WDT Time out period
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Time out Period 64ms 128ms 256ms 512ms 2048ms 8192ms 32768ms 131072ms
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12. LCD Driver The LCD driver contains a controller, a voltage generator, 6 common signal pins and up to 38 segment driver pins. There are three different driving modes: 1/6 duty and 1/3 bias, 1/5 duty and 1/3 bias, 1/4 duty and 1/3 bias, 1/3 duty and 1/2 bias. The driving mode is controlled by Code Option. Also PORTC - PORTF can be used as LCD segment (selected by system register). When the "STOP" instruction is executed, the LCD will be turned off, but the data of LCD RAM is the same as that before the "STOP" instruction is executed. When the LCD is off, both COMMON and SEGMENT output high or low. The OSC will always be the source clock for LCD frame frequency, no matter the CPU system clock is OSC or OSCX. 12.1. LCD Control Register Address $06 Bit3 ENX Bit2 ELON Bit1 LCDOFF Bit0 PSGON Remarks ... Bit1: LCD on/off control ... Bit0: Select CX or LCD segment38 Bit1: Select LCD segment output high or low ... Bit0: Select PORTC or LCD segment Bit1: Select PORTD or LCD segment Bit2: Select PORTE or LCD segment Bit3: Select PORTF or LCD segment Power On 0010
$13
ELF
ELPF
SOH/L
S/CX
0001
$16
O/S4
O/S3
O/S2
O/S1
1111
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LCDOFF: SOH/L: S/CX: O/S4: O/S3: O/S2: O/S1: Notice:
0: LCD on and pump on 1:LCD off 0: When LCD off, COM and SEG output low 1: When LCD off, COM and SEG output high 0: CX 1: SEG38 .com 0: PORTF as I/O 1: PORTF as segment 22 - 25 0: PORTE as I/O 1: PORTE as segment 26 - 29 0: PORTD as I/O 1: PORTD as segment 30 - 33 0: PORTC as I/O 1: PORTC as segment 34 - 37
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1. The LCDOFF (system register 06H bit1) will be set to "1" after reset, and the LCD display will be disabled. 2. The LCD pump circuit may be on or off after Power-on Reset. When LCDOFF (system register $06 bit1) is cleared to "0", the LCD pump circuit will be turned on. It will turn off only after receiving a "STOP" instruction. 3. Setting LCDOFF = 1 disables the LCD display output only, and won't turn off the LCD pump circuit. 4. When the SH67L19 runs in STOP mode, the LCD pump circuit turns off automatically. The user should turn on the LCD pump (set LCDOFF = 0) after the next wake up.
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Example:
Power ON ....... LCD pump on or off Display On (sets LCDOFF = 0 and sets bias )
Starts the LCD pump circuit , and turns on LCD display. Save the total current when only use solar battery. It also can be canceled when system has back-up battery.
HALT LCD pump starts Wakes up after at least 50ms ....... Sets Display Off : ( sets LCDOFF = 1 ) LCD pump ON (whatever display on or off) ....... Sets Display On : ( sets LCDOFF = 0 )
LCD pump off Wake up (By RESET or other INT)
sets LCDOFF = 1 only disable the LCD display, won't turn off the LCD pump.
STOP (Pump turns off automatically)
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.......
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12.2. Configuration of LCD RAM LCD 1/6 duty, 1/3 bias (COM1 - 6, SEG1 - 38) Address 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H 311H Bit3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 Address 330H 331H 332H 333H 334H 335H 336H 337H 338H 339H 33AH 33BH 33CH 33DH 33EH 33FH 340H 341H Bit3 Bit2 Bit1 COM6 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 Bit0 COM5 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18
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Address 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH 31EH 31FH 320H 321H 322H 323H 324H 325H Bit3 COM4 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 Bit2 COM3 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 Bit1 COM2 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 Bit0 COM1 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 Address 342H 343H 344H 345H 346H 347H 348H 349H 34AH 34BH 34CH 34DH 34EH 34FH 350H 351H 352H 353H 354H 355H Bit3 Bit2 Bit1 COM6 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 Bit0 COM5 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38
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12.3. Connection Diagram
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The pump circuit frequency could be 2k and 4k (selected by Code Option).
1. VDD = 1.5V, 4.5V LCD, 1/6 duty, 1/3 bias and 1/5 duty, 1/3 bias and 1/4 duty, 1/3 bias
CUP1 CUP2 VDD 0.1uF VP2 VP2 0.1uF 0.1uF VDD = 1.5V
2.
VDD = 1.5V, 3V LCD, 1/3 duty, 1/2 bias
CUP1 CUP2 VDD 0.1uF VDD = 1.5V
0.1uF (3V) VP1 (3V) GND
LOGIC CIRCUIT
(3V) VP1 (4.5V) GND
LOGIC CIRCUIT
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12.4. LCD Waveform 1/6, 1/5, 1/4 duty, 1/3 bias LCD waveform (VDD = 1.5V, VP1 = 4.5V, VP2 = 3V)
Select VP1 VP2 COMX VDD GND VP1 SEGX Select VP2 Light VDD GND VP1 VP2 SEGX Unselect VDD GND Unlight Unlight Unlight Unselect
1/3 duty, 1/2 bias LCD waveform (VDD = 1.5V, VP1 = VP2 = 3V)
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VP2 COMX VDD GND
Select
Unselect
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VP2 SEGX Select GND VP2 SEGX Unselect VDD Unlight GND Unlight VDD Light Unlight
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13. Interrupt 4 interrupt sources are available on SH67L19: - External interrupt ( INT0 shared with PORTA.0) - Timer0 interrupt (TM0INT) - Base Timer interrupt (BTINT) - PORTB & PORTC falling or rising edge detection interrupt ( INT1 ) The configuration of interrupt's system register: Address $00 $01 Bit 3 IEX IRQX Bit 2 IET0 IRQT0 Bit 1 IEBT IRQBT Bit 0 IEP IRQP Remarks 1: Enable / 0: Disable 1: Request / 0: No request
13.1. The Enable Flags and Request Flags Both the Enable flags and Request flags can be read or written by software. But the Request flags will be set to "1" by the hardware interrupt and the Enable flags will be reset by hardware when the interrupt service routine is entered. 13.2. Interrupt Servicing Sequence Diagram In SH6610C CPU interrupt services routine, the user can enable any interrupt enable flag before returning from an interrupt. The frequently asked question is when the next interrupt would be serviced? Will the nesting interrupt occur? From the servicing sequence timing diagram, if interrupt request is ready and instruction execution N is IE enable, then the interrupt can start right after the next two instructions: I1 or instruction I2 disable the interrupt request or enable flag, and then the interrupt service sequence would be terminated. 13.3. External Interrupt ( INT0 )
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External interrupt is shared with the PORTA.0 (falling or rising edge active). When the bit 3 of the register $0 (IEX) is set to "1", the external interrupt is enabled, and only PORTA.0 at input mode will generate external interrupt. 13.4. Timer 0 Interrupt (T0INT), Base Timer Interrupt (BTINT), Port Interrupt ( INT1 ) If IET0 = 1, the overflow of timer 0 will create the interrupt of timer 0. If IEBT = 1, the overflow of the Base timer will create the interrupt of the Base timer. If IEP = 1, the falling or rising edge of every port in PORTB&C will create INT1 interrupt (The condition is PORTB, C at input mode).
Inst. cycle
1
2
3
4
5
Instruction Execution N
Instruction Execution I1
Instruction Execution I2
Interrupt Generated
Interrupt Accepted
Vector Generated Stacking
Fetch Vector address Reset IE.X
Start at vector address
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SH67L19
14. Resistor to Frequency Converter Address $06 $07 $269 $26A $26B $26C $26D Bit 3 ENX O/RF RF1.3 RF2.3 RF3.3 RF4.3 RF5.3 Bit 2 ELON RX3EN RF1.2 RF2.2 RF3.2 RF4.2 RF5.2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W Remarks ... Bit3: R-F convert counter on/off control Bit0 - 2: count resister1 - 3 enable Bit3: set PORTB as R-F converter R-F counter register nibble 1 (bit0 - 3) R-F counter register nibble 2 (bit4 - 7) R-F counter register nibble 3 (bit8 - 11) R-F counter register nibble 4 (bit12 - 15) R-F counter register nibble 5 (bit16 - 19) Power On 0010 0000 0000 0000 0000 0000 0000
LCDOFF PSGON RX2EN RF1.1 RF2.1 RF3.1 RF4.1 RF5.1 RX1EN RF1.0 RF2.0 RF3.0 RF4.0 RF5.0
When we set O/RF = 1, Port B is used as R-F converter. It's like a RC oscillation circuit, and uses the 20-bit counter to get the resistive value of the sensor. First to set RX1EN = 1 (enable RX1-F convert), and then start timer1 or timer0 counter and set ENX = 1 (start R-F counter). When the timer INT occurs, we can get the value of the RX1-F counter. So, we can get different count values of R-T, R-H, R-ref by setting RX1EN, RX2EN, RX3EN = 1 in turn. The R-F converter could keep on working in HALT mode, and would stop automatically when the "STOP" instruction is executed. (Keep the last state of RX1-3 ports and stop the R-F counter.)
O/RF RX1EN R-T RX1 (PORTB.0)
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RX2EN
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R-H RX2 (PORTB.1)
RX3EN ENX R-ref RX3 (PORTB.2)
16 BIT COUNTER
CX FIN CX
RXB (PORTB.3)
R-F CONVERTER
The SH67L19 provides two methods for R-F's application to improve the performance of R-F applications (selected by Code Option). When designing the R-F's peripheral circuit, we can select the capacitor connected with CX and PORTB.3 or CX and GND. Note: the method of the capacitor connection must match the corresponding Code Option. Temperature sensor resistor: 10k - 50k @25 (for reference only) Humidity sensor: 60k @25, 50%RH (for reference only) Notice: 1. When the O/RF is set to "1", PORTB interrupt will be disabled. 2. Connect CX to VDD or GND when the R-F converter is not used. 3. The 20-bit counter can be used as an event counter when not using the R-F converter. 4. Max-frequency of R-F converter should be less than 2MHz.
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SH67L19
15. EL-LIGHT Address $06 Bit 3 ENX Bit 2 ELON Bit 1 Bit 0 R/W R/W Remarks Bit0: PSG on/off control Bit1: LCD on/off control Bit2: EL-light on/off control Bit3: R-F convert counter on/off control Bit0: Set CX as LCD segment 38 Bit1: Select LCD segment output high or low EL-LIGHT mode control Bit2: ELP driver output frequency control Bit3: EL-LIGHT driver frequency select Power On 0010
LCDOFF PSGON
$13
ELF
ELPF
HLM
S/CX
R/W
0001
ELPF: (frequency of ELP pin charge waveform) 0 ELCLK 1 ELCLK/2 (ELCLK = 32kHz@32kHz Oscillator or 131kHz/4@131kHz RC Oscillator by Code Option.) ELF: (frequency of ELC pin discharge waveform) 0 ELCLK/64 1 ELCLK/32 Set the system register $13 to select the EL-LIGHT driver waveform. Setting ELON = 1 will turn on the EL-LIGHT driver. The ELC and ELP will output driver waveform automatically as shown in the following diagram. With externally transistor, diode, inductance and resistor, we can pump the EL panel to AC 100 - 250V.
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VDD
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L1 D1 R1 Q1 R2 Q2 R3 EL PANEL
ELON
ELP
EL-LIGHT DRIVER
ELC
ELC
ELP
ELP: Output for EL charge ELC: Output for EL discharge
While the EL-LIGHT is turned on, the ELC will be turned on before ELP is on. When the EL-LIGHT is turned off, the ELP will turn off first, then ELC will still work for one cycle to make sure that there is no voltage left on EL panel. The EL-LIGHT would keep on working in HALT mode. But it would turn off after the "STOP" instruction is executed (ELC & ELP keep low). Notice: 1. When PORTA.0 and PORTA.3 are used as EL drivers, the data of PA.0 & PA.3 must be clear to "0". 2. Please turn on the HLM (heavy-load mode) before turning on the EL-LIGHT. 3. Please turn off the EL-LIGHT before executing the "STOP" instruction.
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SH67L19
16. Options Bonding options System registers $15 bit1, bit0 are reserved for users. It is available for system developer to select 2 bonding options, and the user programs to select a subprogram. B1 0 1 0 1 B0 0 0 1 1 B1 bond to GND and B0 bond to VDD B0 bond to VDD B1 bond to GND Remarks R/W R R R R
VDD
GND B1 B0 GND B1
VDD
B0
PCB
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B1 = 1
B0 = 0
B1 = 1
B0 = 1
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VDD
GND B1 B0 GND B1
VDD
B0
PCB
B1 = 0
B0 = 0
B1 = 0
B0 = 1
SH67L19 Bonding Option 17. STOP/HALT Mode STOP/HALT Mode STOP (STOP instruction) Oscillator OSC stop OSCX Stop CPU core Hold Wake up RESET, INT0 , INT1 Executing after Wake up (a) If RESET signal valid, system will reset. (b) If INT0 , INT1 signal valid, system will enter interrupt subroutine, then execute the main program to continue. (a) If RESET signal valid, system will reset.
OSC active HALT (HALT instruction) OSCX active if OSCX is on
Hold
RESET, INT0 , T0IN, (b) If INT0 , INT1 , T0INT, BTINT signal valid, system will enter interrupt subroutine first, then execute the main INT1 , BTINT program to continue.
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SH67L19
18. Instruction Set All instructions are one-cycle and one-word instructions with characteristic in memory-oriented operation. Arithmetic and Logical Instruction Accumulator Type Mnemonic ADC ADCM ADD ADDM SBC SBCM SUB SUBM EOR EORM OR X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) Instruction Code 00000 0bbb xxx xxxx 00000 1bbb xxx xxxx 00001 0bbb xxx xxxx 00001 1bbb xxx xxxx 00010 0bbb xxx xxxx 00010 1bbb xxx xxxx 00011 0bbb xxx xxxx 00011 1bbb xxx xxxx 00100 0bbb xxx xxxx 00100 1bbb xxx xxxx 00101 0bbb xxx xxxx 00101 1bbb xxx xxxx 00110 0bbb xxx xxxx 00110 1bbb xxx xxxx 11110 0000 000 0000 AC Function Mx + Ac + CY Flag Change CY CY CY CY CY CY CY CY
AC, Mx Mx + Ac + CY AC Mx + Ac
AC, Mx Mx + Ac AC Mx + -Ac + CY
AC, Mx Mx + -Ac + CY AC Mx + -Ac + 1
AC, Mx Mx + -Ac + 1 AC Mx Ac
AC, Mx Mx Ac AC AC, Mx Mx | Ac Mx | Ac Mx & Ac
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ORM AND ANDM SHR
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AC, Mx
AC
Mx & Ac 0 AC [3] ; AC [0] CY ; AC shift right one bit
CY
Immediate Type Mnemonic ADI ADIM SBI SBIM EORIM ORIM ANDIM X, I X, I X, I X, I X, I X, I X, I Instruction Code 01000 i i i i xxx xxxx 01001 i i i i xxx xxxx 01010 i i i i xxx xxxx 01011 i i i i xxx xxxx 01100 i i i i xxx xxxx 01101 i i i i xxx xxxx 01110 i i i i xxx xxxx AC Function Mx + I Flag Change CY CY CY CY
AC, Mx Mx + I AC Mx + -I + 1
AC, Mx Mx + -I + 1 AC, Mx Mx I AC, Mx Mx | I AC, Mx Mx & I
Decimal Adjust Mnemonic DAA DAS X X Instruction Code 11001 0110 xxx xxxx 11001 1010 xxx xxxx Function AC; Mx Decimal adjust for add. AC; Mx Decimal adjust for sub. Flag Change CY CY
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SH67L19
Transfer Instruction Mnemonic LDA STA LDI X (, B) X (, B) X, I Instruction Code 00111 0bbb xxx xxxx 00111 1bbb xxx xxxx 01111 i i i i xxx xxxx AC Mx Function Mx AC I Flag Change
AC, Mx
Control Instruction Mnemonic BAZ BNZ BC BNC BA0 BA1 BA2 X X X X X X X X X H, L Instruction Code 10010 xxxx xxx xxxx 10000 xxxx xxx xxxx 10011 xxxx xxx xxxx 10001 xxxx xxx xxxx 10100 xxxx xxx xxxx 10101 xxxx xxx xxxx 10110 xxxx xxx xxxx 10111 xxxx xxx xxxx PC PC PC PC PC PC PC PC ST Function X X X X X X X X if AC = 0 if AC 0 if CY = 1 if CY 1 if AC (0) = 1 if AC (1) = 1 if AC (2) = 1 if AC (3) = 1 Flag Change
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BA3 CALL RTNW RTNI HALT STOP JMP TJMP NOP Where PC AC -AC CY Mx
11000 xxxx xxx xxxx.com PC X (Not include p) 11010 000h hhh l l l l 11010 1000 000 0000 11011 0000 000 0000 11011 1000 000 0000 PC ST; TBR hhhh; AC l l l l CY; PC ST CY
CY; PC + 1
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X
1110p xxxx xxx xxxx 11110 1111 111 1111 11111 1111 111 1111
PC PC
X (Include p) (PC11-C8) (TBR) (AC)
No Operation
Program counter Accumulator Complement of accumulator Carry flag Data memory
I | & bbb
Immediate data Logical exclusive OR Logical OR Logical AND RAM bank = 000
p ST TBR
ROM page = 0 Stack Table Branch Register
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SH67L19
Absolute Maximum Rating*
DC Supply Voltage . . . . . . . . . . . . . . . -0.3V to +3.0V Input Voltage . . . . . . . . . . . . . .. -0.3V to VDD + 0.3V Operating Ambient Temperature . . .. -10 to +60 Storage Temperature . . . . . . . . . . . . -55 to +125 DC Electrical Characteristics (VDD = 1.5V, GND = 0V, TA =25C, fosc = 32.768kHz crystal, foscx is off, unless otherwise specified) Parameter Operating Voltage Operating Current Standby Current 1 Standby Current 2 Symbol VDD IOP ISB1 ISB2 VIH1 VIH2 VIL1 VIL2 VOH1 VOL1 VOH2 Min. 1.2 0.8 X VDD 0.85 X VDD GND - 0.3 GND - 0.3 0.8 X VDD 0.8 X VDD Typ. 1.5 4 2 Max. 1.7 6 3 0.5 VDD + 0.3 VDD + 0.3 0.2 X VDD 0.15 X VDD 0.2 X VDD Unit V A A A V V V V V V V Conditions All output pins unload execute NOP instruction, exclude LCD, EL, PSG, R-F & Alarm current All output pins unload (HALT mode) exclude LCD current. (Not in heavy load mode) All output pins unload (STOP mode), LCD off PORTA - PORTF, OSCI, OSCXI (Driven by external clock) (reference only) INT0 , RESET , TEST, CX (schmitt trigger input)
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability DC Electrical Characteristics
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Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Output High Voltage Output Low Voltage Output High Voltage
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PORTA - PORTF, OSCI, OSCXI (Driven by external clock) (reference only) INT0 , RESET , TEST, CX, (schmitt trigger input) PORTC - PORTF (IOH = -0.3mA) PORTC - PORTF (IOL = 0.3mA) PORTA.1, PORTA.2 as PSG output, PORTA.0, PORTA.3 as EL driver, IOH = -0.3mA PORTA.1, PORTA.2 as PSG output, PORTA.0, PORTA.3 as EL driver, IOL = 0.3mA PORTB as R-F (IOH = -2.4mA) VDD=1.2V PORTB as R-F (IOL = 2.4mA) VDD=1.2V SEGX, IOH = -3A SEGX, IOL = 3A COMX, IOH = -8A COMX, IOL = 8A
Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Pull-high/pull-low Resistor Pull-high Resistor LCD Lighting
VOL2 VOH3 VOL3 VOH4 VOL4 VOH5 VOL5 RP1 RP2 ILCD
0.8 X VDD VP1 - 0.2 VP1 - 0.2 -
150 250 -
0.2 X VDD 0.2 X VDD 0.2 0.2 1
V V V V V V V k k A
Pull-high/pull-low resistor for PORT (IOH = -6A; IOL = 6A) Pull-high resistor for RESET pin No panel loaded. LCD pump frequency = 4k
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SH67L19
DC Electrical Characteristics (VDD = 1.5V, GND = 0V, TA = 25C, fosc = 131kHz RC, foscx is off, unless otherwise specified) Parameter Operating Voltage Operating Current Standby Current Standby Current Reset Current Symbol VDD IOP ISB1 ISB2 IREST Min. 1.2 Typ. 1.5 7 3 Max. 1.7 10 5 0.5 20 Unit V A A A A Conditions All output pins unload execute NOP instruction, exclude LCD, EL, PSG, R-F & Alarm current All output pins unload (HALT mode) exclude LCD current. (Not in heavy load mode) All output pins unload (STOP mode), LCD off Reset current
DC Electrical Characteristics
(VDD = 1.5V, GND = 0V, TA = 25C, foscx = 500kHz RC or 455kHz ceramic, fosc is on, unless otherwise specified) Parameter Operating Voltage Operating Current Standby Current Symbol VDD IOP ISB1 ISB2 Min. 1.2 Typ. 1.5 30 20 Max. 1.7 50 25 0.5 Unit V A A A Conditions All output pins unload execute NOP instruction, exclude LCD, EL, PSG, R-F & Alarm current All output pins unload (HALT mode) exclude LCD current. (Not heavy load mode) All output pins unload (STOP mode), LCD off
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Standby Current AC Characteristics
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(VDD = 1.5V, GND = 0V, TA = 25C, fosc = 32.768kHz crystal, unless otherwise specified) Parameter Oscillation Start Time AC Characteristics (VDD = 1.5V, GND = 0V, TA = 25C, fosc = 131kHz RC, unless otherwise specified) Parameter Frequency Variation (RC) AC Characteristics (VDD = 1.5V, GND = 0V, TA = 25C, foscx = 500kHz RC, unless otherwise specified) Parameter Frequency Variation (RC) Symbol f/f Min. Typ. Max. 30 Unit % Conditions Include supply voltage and chip to chip variation Symbol f/f Min. Typ. Max. 30 Unit % Conditions Include supply voltage and chip to chip variation Symbol tOST Min. Typ. 1 Max. 2 Unit s Conditions -
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SH67L19
Typical RC Oscillator Resistor (OSC) vs. Frequency: (VDD = 1.5V, for reference only)
VDD = 1.5V fosc (kHz) 200.0 150.0 100.0 50.0 0.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0R (M)
Typical VDD vs. Frequency of RC Oscillator (OSC): (for reference only)
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fosc (kHz)
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132.0 131.0 130.0 129.0 128.0 127.0 126.0 1.2 1.3 1.4
1.5
1.6
1.7
1.8
VDD (V)
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SH67L19
Typical RC Oscillator Resistor (OSCX) vs. Frequency: (VDD = 1.5V, for reference only)
VDD = 1.5V foscx (kHz) 700 600 500 400 300 200 100 0.20
0.70
1.20
1.70
R (M)
Typical VDD vs. Frequency of RC Oscillator (OSCX): (for reference only)
foscx (kHz)
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660 650 640 630 620 610 600 590 1.2 1.3 1.4 1.5 1.6
R = 360k
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1.7
1.8
VDD (V)
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SH67L19
Code Option:
Body data: 0110 1010 0000 1001 (67L19) Data: CLDT PRAF 0000 0000 CL (OSC clock source) 0, 0: fOSC = 32.768kHz Crystal (Default) 0, 1: fOSC = 32kHz RC 1, x: fosc = 131kHz RC DT (LCD duty selection) 0, 0: 1/6 duty (Default) 0, 1: 1/5 duty 1, 0: 1/4 duty 1, 1: 1/3 duty P (LCD Pump circuit frequency) 0: 2kHz (Default) 1: 4kHz R (internal pull high for RESET selection) 0: internal pull high enable (Default) 1: internal pull high disable
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A (alarm carrier frequency) 0: 4kHz (Default) 1: 2kHz F (R-F application's selection) 0: The capacitor connect with CX and PORTB.3 (Default) 1: The capacitor connect with CX and GND
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SH67L19
Application Circuits (for reference only)
SH67L19 chip substrate connects to system ground. AP1: VDD = 1.5V (Solar battery) OSC: RC: 131kHz (Code Option) LCD: 4.5V, 1/6 duty, 1/3 bias PORTA, PORTB: I/O; PORTC - PORTF used as segment; CX used as segment
6 X 38 LCD Solar Battery
0.1uF LED VDD CUP1, 2 0.1uF 0.1uF VP2 VP1
OSCI 1.4M 10 - 100K RESET CX
SH67L19
PORTA
PORTB
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0.1uF
GND TEST
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AP2: VDD = 1.5V OSC: 32.768kHz crystal (Code Option) LCD: 4.5V, 1/6 duty, 1/3 bias PORTA.1, PORTA.2: PSG output PORTA.0, PORTA.3: EL-LIGHT driver PORTB: I/O; CX, PORTC - PORTF: Segment
20KEY
6 X 37 LCD
0.1uF VDD VDD 0.1uF X 2 10 - 100K VP2 PORTA.2 VP1 3.2mH/ 15 CUP1, 2 PORTA.1 100
BUZZER
VDD
0.1uF 32768Hz 12p 12p
RESET
SH67L19
PORTA.0 (ELP) PORTA.3 (ELC) 1N4148 Q1
EL-PANEL 10K Q2
OSCI OSCO GND TEST
PORTB
I/O
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SH67L19
AP3: VDD = 1.5V OSC: 32.768kHz crystal (Code Option) LCD: 4.5V, 1/6 duty, 1/3 bias PORTA.1, PORTA.2: PSG output PORTA.0, PORTA.3: I/O PORTB, CX: R-F Converter PORTC - PORTF: Segment
6 X 37 LCD
0.1uF VDD VDD 0.1uF X 2 10 - 100k VP2 PORTA.2 VP1 RX1 0.1uF 32.768kHz 12p OSCI OSCO CX RXB CX RESET R-T R-H R-F 1k CUP1, 2 PORTA.1 100
BUZZER
SH67L19
RX2 RX3
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12p GND TEST
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R-H: Humidity Sensor CX: R-F converter capacitor
R-T: Temperature Sensor R-F: Reference Resister AP4: VDD = 1.5V OSC: Crystal oscillator 32.768kHz (Code Option) OSCX: Ceramic oscillator 455kHz PORTB: I/O; PORTA.1, PORTA.2: ALARM output LCD: 3V, 1/3 duty, 1/2 bias
3 X 38 1/8 duty 1/4 bias
VDD
47p
VDD
10 - 100k 0.1uF 0.1uF
OSCXI 455kHz OSCXO 47p 100 PORTA.1 BUZZER
RESET
SH67L19
VP2 VP1 I/O 12p
32.768kHz
PORTB OSCO OSCI TEST
PORTA.2
12p
GND
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SH67L19
Bonding Diagram
PORTD.3 PORTE.0 PORTE.1 PORTE.2 PORTE.3 PORTF.0 PORTF.1 PORTF.2 PORTF.3 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 47 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM6 COM5 COM4 COM3 46 45 44 43 42 41
(0,0)
1 PORTD2 PORTD1 PORTD0 PORTC3 PORTC2 PORTC1 PORTC0 CX PORTA3 PORTA2 PORTA1 PORTA0 PORTB3 PORTB2 PORTB1 PORTB0 2 3 4 5 6 7 8 9 10 11 12 13
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
SH67L19
Y
X
40 39 38 37 36 35 34 33 32
2132 um
14 15 16 17
B0 18
19 20 21 22 B1 24 25 26 27 28 29 30 31 CUP1 OSCXO OSCXI CUP2 VP2 RESET VP1 OSCO COM1 COM2 OSCI GND TEST
23
VDD
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2116 um
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Pad Location
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Designation PORTD.3 PORTD.2 PORTD.1 PORTD.0 PORTC.3 PORTC.2 PORTC.1 PORTC.0 CX PORTA.3 PORTA.2 PORTA.1 PORTA.0 PORTB.3 PORTB.2 PORTB.1 PORTB.0 B0 VDD OSCO X -988 -988 -988 -988 -988 -988 -988 -988 -988 -988 -988 -988 -988 -924.4 -924.4 -924.4 -924.4 -603 -503 -373
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Y 996 866 749 632 515 398 281 164 47 -70 -187 -304 -421 -562.8 -703 -818 -958.2 -966 -966 -964 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Pad No. 20 21 22 Designation OSCI OSCXO OSCXI B1 GND RESET TEST CUP1 CUP2 VP2 VP1 COM1 COM2 COM3 COM4 COM5 COM6 SEG1 SEG2 SEG3 X -263 -153 -43 67 67 177 289 401 513 625 737 857 988 988 988 988 988 988 988 988
unit: m
Y -964 -964 -964 -996 -896 -996 -996 -996 -996 -996 -996 -996 -996 -862.5 -747.5 -632.5 -517.5 -402.5 -287.5 -172.5
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SH67L19
Pad Location (continued)
Pad No. 39 40 41 42 43 44 45 46 47 48 49 50 51 Designation SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 X 988 988 988 988 988 988 988 988 988 988 855 741 627 Y -57.5 57.5 172.5 287.5 402.5 517.5 632.5 747.5 862.5 996 996 996 996 Pad No. 52 53 54 55 56 57 58 59 60 61 62 63 64 Designation SEG17 SEG18 SEG19 SEG20 SEG21 PORTF.3 PORTF.2 PORTF.1 PORTF.0 PORTE.3 PORTE.2 PORTE.1 PORTE.0 X 513 399 285 171 57 -57 -171 -285 -399 -513 -627 -741 -855 Y 996 996 996 996 996 996 996 996 996 996 996 996 996
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SH67L19
Ordering Information
Part No. SH67L19H Package CHIP FORM
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Data Sheet Revision History
Version 1.0 Original Content Date Dec. 2004
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